This invention relates in general to the field of circuit cells in an integrated circuit, and particularly to a cell layout utilizing boundary cells with mixed poly pitch within the integrated circuit.
As known in the art, when engineers design a complex integrated circuit, such as a microprocessor, a hierarchical approach is typically used. The design is broken down into high-level pieces that connect together to form the design. The high-level pieces are further broken down into yet smaller pieces that connect together to form the high-level pieces. This hierarchical breakdown may continue such that there are several levels in the hierarchy. The hierarchical approach has the advantage of making the complexity of the design manageable and achievable. The hierarchical approach also has the advantage of enabling different engineers to design different pieces of the design.
At the highest level, the design is made up of multiple pieces commonly referred to as “functional blocks” that are connected together to form the integrated circuit. For example, a microprocessor is made up of functional blocks such as arithmetic logic units, register files, cache memories, floating-point units, instruction translators, etc. The functional blocks have inputs and outputs that are coupled together to form the microprocessor design. Each of the functional blocks is made up of multiple smaller pieces commonly referred to as “cells.” Examples of cells are logic gates, (e.g., AND, OR, NAND, NOR), flip-flops, multiplexers, registers, comparators, counters, etc. The cells have inputs and outputs that are coupled together to form a functional block. The cells may be standard cells chosen from a library of common cells. When engineers design a block, they typically focus first on which cells need to be included in the block and how the cells in the block will be connected logically, that is, which inputs will be connected to which outputs. Next, they focus on how the included cells will be physically placed within the block and how their inputs and outputs will be connected physically.
Typically, there are two methods of physically placing the cells within a functional block. One is for the designers themselves to physically place the cells within the functional block. This type of functional block is commonly referred to as a custom block. An example of a custom block is a high-density memory cell, such as a dynamic random access memory (DRAM) cell. The other method of physically placing the cells of a functional block is to employ computer-aided design software tools. These tools are commonly referred to as auto-place-route (APR) tools, and functional blocks whose placement is performed by APR tools are commonly referred to as APR blocks. APR tools take as input the list of cells that make up the block (including their physical area and input/output specifications), information that specifies how the cells are to be connected together, and a boundary of the block within which the tool is to place the cells.
With the increasing down-scaling of integrated circuits, the integrated circuits become more compact, and some restricted design rules have to be applied, which have become major limitations in the layout design. For standard cells that are frequently used in the integrated circuits, these restricted design rules cause the increase in the chip area usage, increased difficulty in the auto placement and route, and the violation in the design rule check.